Methods and apparatus for providing a negative delay on an IC chip

ABSTRACT

An integrated circuit chip on which a relatively large on-chip delay is provided using a relatively small delay in conjunction with a phase-locked-loop, whereby the relatively large variations typical of large on-chip delays are avoided.

BACKGROUND OF THE INVENTION

The present invention is generally directed to improved methods andapparatus for controlling the timing of signals provided on anintegrated circuit (IC) chip.

As is well known, in designing digital logic circuitry for use on an ICchip, there often arises a need for additional timing edges besidesthose provided by a standard system clock. This is particularly true forIC chip designs which utilize memory structures (RAM, ROM, etc.). Theseadditional timing edges may typically take the form of clocks which arerequired to switch at times other than the standard system clock.

The need to provide these additional timing edges creates a problem withrespect to IC chips, particularly VLSI (very large scale integrated)circuit chips where it is desirable to compact as much as possible ontothe chip. This problem arises because of the difficulties involved inaccurately providing such additional timing edges on a VLSI chip.

Typically, additional timing edges are provided on an IC chip bydelaying the standard system clock by a prescribed amount usingserially-connected inverters or other active delay elements formed onthe chip. These active on-chip delays are severely affected byunpredictable processing variations as well as by voltage andtemperature, which can cause the resulting delay to vary by as much as±60%. Thus, when a large delay is required to be provided on anintegrated circuit chip, this ±60% variation may not be tolerable. Atypical known solution is to provide this required long delay circuitryoff-chip where accuracy can be more precisely controlled. However, thishas the severe disadvantage of requiring more parts, more board space,and more expense.

An example of the problem associated with providing a relatively longon-chip delay on an IC chip is illustrated by the graphs in FIG. 1.

Graph A in FIG. 1 illustrates a typical standard system clock C having aclock cycle time T with rising clock edges occurring at times T1 and T3,and falling clock edges occurring at times T2 and T4.

Graph B in FIG. 1 illustrates a FIRST DELAYED CLOCK C1 produced by anon-chip delay d1 providing a relatively small delay (e.g., d1=0.10 T).It is assumed in Graph B that d1 varies by about ±40% of d1, asindicated by Δd1.

Graph C in FIG. 1 illustrates a SECOND DELAYED CLOCK C1 produced by anon-chip delay d2 providing a relatively large delay (e.g., d2=0.90 T).Similar to d1 in Graph B, it is assumed in Graph C that d2 varies byabout ±40% of d2, as indicated by Δd2.

As shown by Graph B in FIG. 1, the effect of Δd1 on the timing edgesprovided by C1 is relatively small and can easily be tolerated. Thiswill be evident by noting that, for d1=0.10 T, Δd1 will only amount toabout 0.08 T.

However, as shown by Graph C in FIG. 1, the effect of Δd2 on the timingedges of C2 is intolerable, since it can cause the rising edge of C2 tooccur in the next clock cycle (after T3). This will be evident by notingthat, for d2=0.90 T, Δd2 will amount to about 0.72 T. This will causethe rising clock edge of C2 to occur at about 1.26 T (0.90 T+0.36 T),which is greater than the clock cycle time T, as illustrated in Graph C.Note that this occurred assuming that Δd2 varies by ±40% Since thisvariation may typically be ±60% in the worst case, the provision ofother than relatively small delays on a chip can present a seriousproblem. This is a primary reason why the prior art normally providesrelatively long delays (such as those greater than T/2) off-chip wheredelay variations can be better controlled.

SUMMARY OF INVENTION

A broad object of the present invention is to provide improved methodsand apparatus for creating chip delays on an IC chip.

A more specific object of the present invention is to provide improvedmethods and apparatus for creating a relatively large on-chip delay on aIC chip having significantly less variability than heretofore possible.

Another object of the present invention is to provide improved methodsand apparatus for creating clock signals on an IC chip having edgeswhich occur at different times from normally available clock edges.

A further object of the present invention in accordance with one or moreof the foregoing objects is to provide the aforementioned methods andapparatus in an efficient and economical manner.

In a preferred embodiment of the present invention directed toaccomplishing the above objects, a significant technical advance isobtained by advantageously creating a "negative" on-chip delay which canbe used as a substitute when a large delay (such as greater than T/2) isrequired, whereby delay variations are maintained within tolerablelimits, even for relatively large delays.

The specific nature of the invention as well as other objects,advantages and uses thereof will become evident from the followingdescription of a preferred embodiment of the invention in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a series of graphs illustrating problems that can occur usingknown on-chip delays for creating timing signals.

FIG. 2 is a block diagram illustrating how delays are conventionallyprovided on an IC chip.

FIG. 3 is a series of graphs illustrating the delays produced by FIG. 2.

FIG. 4 is a block diagram illustrating a preferred embodiment of thepresent invention for creating a relatively long delay on an IC chip.

FIG. 5 is a series of graphs illustrating the operation of FIG. 4.

DESCRIPTION OF PREFERRED EMBODIMENTS

Like numerals and characters represent like elements throughout thefigures of the drawings.

Referring to FIG. 2, shown therein is a block diagram illustrating howdelays are typically provided on an IC chip, such as a VLSI chip. Asindicated in FIG. 2, the chip includes a RAM (random access memory) 14,a flip-flop 16 and a latch 18. Of course, other circuitry is alsoprovided on the chip, but is not shown since it is not pertinent to thepresent invention.

It will be assumed that RAM 14 in FIG. 2 requires the normal systemclock C, that flip-flop 16 requires a clock C' having a rising edgewhich occurs a relatively short time d' after the rising edge of systemclock C, and that latch 18 requires a clock C" having a rising edgewhich occurs a relatively long time d" after the rising edge of systemclock C. The delay d' required for clock C' may typically be provided byan on-chip delay 20, and the delay d" required for clock C" maytypically be provided by an on-chip delay 22. Graphs A, B and C in FIG.3 respectively illustrate system clock C, flip-flop clock C' and latchclock C" provided by FIG. 2, and the delays d' and d" provided for C'and C", respectively.

Since the delay d' of delay 20 in FIG. 2 is relatively short, its worstcase variations can be tolerated, as previously explained with respectto the first delayed clock C1 in FIG. 1. However, since delay d" ofdelay 22 is relatively long, its worst case variations could create theproblem illustrated for the SECOND DELAYED CLOCK C2 in Graph C of FIG.1, which illustrates how this worst case delay can cause the rising edgeof the delayed clock to occur in the wrong clock cycle. One way ofpreventing this problem from occurring is to test delay 22 on each chipto make sure that its actual worst-case delay variation is withinacceptable limits. This added testing is undesirable since it cansignificantly increase the manufacturing cost. Another way of solvingthis problem is to provide this relatively long delay 22 off-chip, whichis also undesirable, as pointed out previously.

FIG. 4 illustrates a preferred embodiment of the invention whichprovides a unique solution to the above described problem of providingan on-chip long delay by creating an on-chip "negative" delay on thechip which can be used instead of a required long delay when its worstcase variations could cause a problem.

With reference to FIG. 4, illustrated therein is the same RAM 14,flip-flop 16 and latch 18 shown in FIG. 2. However, an importantdifference is the manner in which the long delay d" illustrated in GraphC of FIG. 3 is provided for latch 18.

As shown in FIG. 4, the system clock C is applied to a phase-locked-loop(PLL) 25, which may be of conventional form. PLL has inputs 25a and 25band an output 25c. The system clock C is applied to input 25a and afeedback clock signal C_(f) is applied to input 25b. As is well known, aPLL exhibits the characteristic of automatically adjusting its phase sothat signals applied to its inputs 25a and 25b are synchronized.Accordingly, PLL 25 will operate to synchronize the feedback clocksignal C_(f) with the system clock C. This feedback clock signal C_(f)as well as system clock C may thus be used where a normal system clock Cis required, such as for application to RAM 14.

Still with reference to FIG. 4, output 25c of PLL 25 is applied to adelay 28 whose output passes through clock buffer path 42 to become theclock C_(f) applied to RAM 14. As is conventional, this clock bufferpath 42 includes inverters 30 which are used to permit the signalapplied thereto to drive a plurality of other lines, such as generallyindicated by lines 32. For simplicity of illustration, those lines 32which are directed to other chip circuitry not pertinent to the presentinvention are shown terminated with dashes. As explained previously, PLL25 causes C_(f) to. be synchronized with the system clock C, therebymeeting the requirement that RAM 14 receive the system clock C.

So far, it has been described how a clock C_(f) synchronized with thesystem clock C is provided for RAM 14 by the synchronizing operationprovided by PLL 25. It will next be described how clocks C' and C" areprovided by FIG. 4 for flip flop 16 and latch 18, respectively.

As shown in FIG. 4, clock C' is provided for flip flop 16 by passing theoutput of delay 28 to flip flop 16 via delay 20 and a clock buffer path44 including inverters 30. Clock buffer path 44 is chosen to provide thesame delay as path 42. As a result, clock C' will be delayed from clockC_(f) (system clock C) by the delay provided by delay 20, since otherdelays (paths 42 and 44) are the same. The relatively small delay d'required by flip flop 16 is thus provided by choosing delay 20 equal tod'. Since d' is relatively small, it can be provided on-chip since itsworst case variations will be tolerable, as explained previously.

Next to be described is the manner in which the preferred embodiment ofFIG. 4 provides for on-chip implementation of the relatively long delayd" required between clock C" applied to latch 16 and clock C_(f) (systemclock C) applied to RAM 14, despite worst case delay variations whichwould ordinarily make such an on-chip implementation intolerable.

As shown in FIG. 4, clock C" applied to latch 18 is obtained from PLLoutput 25c via clock buffer path 46. This clock buffer path 46, likepath 44, is chosen to be equal to clock buffer path 42 located betweenthe output of delay 28 and RAM 14. Clock C_(f) (the system clock C) willthus be delayed from C" by the amount of delay 28, since other delays(path 42 and 46) are the same. This permits the required relatively longdelay d" for clock C" to be provided by choosing delay 28 equal to d_(n)=T-d", where T equals the clock period. For example, for a requiredrelatively long delay d"=0.90 T, delay 28 need merely provide therelatively small on-chip delay d_(n) =T-0.90 T/10=0.10 T, which would betolerable even in view of worst case variations.

The operation of FIG. 4 is illustrated by the graphs of FIG. 5. Graph Ain FIG. 5 illustrates the system clock C which is applied to input 25aof PLL 25. Graph A also illustrates feedback clock C_(f) which isapplied to PLL input 25b, since PLL 25 synchronizes C_(f) with C. Therequirement that the system clock C be applied to RAM 14 is thus met.

Graph B in FIG. 5 illustrates clock C' applied to flip-flop 16 whichwill be seen to be delayed by delay d'from the system clock C as aresult of being applied thereto via delay 20 and clock buffer path 44.As mentioned previously, since the required delay d' is relativelysmall, its provision on-chip is tolerable.

Graph C in FIG. 5 illustrates clock signal C₂₅ appearing on PLL output25c. Graph D in FIG. 5 illustrates the clock C₂₈ obtained after C₂₅ isdelayed by delay 28. Note in Graphs C and D that, as is to be expected,C₂₈ is delayed from C₂₅ by d_(n), the delay provided by delay 28. Withrespect to the delay d_(p) shown between clock C₂₅ and the system clockC in Graphs A and B in FIG. 5, it will be understood that delay d_(p)represents the delay required to be provided by PLL 25 in order toproduce synchronism between C and C_(f) , as explained previously.

Graph E in FIG. 5 illustrates the resulting clock signal C" appearing atlatch 16 in FIG. 4. It will be remembered that latch 16 requires therelatively long delay d" with respect to the system clock C (Graph C inFIG. 3). It will be understood from Graph E of FIG. 5 that this delay d"is obtained for clock C" as a result of the embodiment of FIG. 4 havingprovided the negative delay d_(n) for C" with respect to the systemclock C, which is equivalent to having provided the relatively longdelay d" using delay 22 in FIG. 2.

Although the present invention has been described with respect toparticular preferred embodiment, it is to be understood that variousmodifications in construction and arrangement are possible within thescope of the invention. Accordingly, the present invention is to beconsidered as including all modifications and variations coming withinthe scope of the invention as defined by the appended claims.

What is claimed is:
 1. An integrated circuit chip comprising:means forproviding a system clock having a predetermined clock period; a firstcomponent which requires said system clock; a second component having aninput which requires a clock having a relatively large delay withrespect to said system clock, said relatively large delay being at leastgreater than one-half of said clock period; a phase-locked-loop havingtwo inputs and an output, one input being coupled to said system clockand the other input being coupled to said input of said first component,said phase-locked-loop being operative to synchronize the input signalsapplied thereto: a delay element providing a delay substantially equalto the difference between said clock period and said large delay; meansfor coupling the output of said phase-locked-loop to said input of saidfirst component via a first path including said delay element; and meansfor coupling the output of said phase-locked-loop to said secondcomponent via a second path which does not include said delay element;said first and second paths providing the same delay except for saiddelay element.
 2. The integrated circuit chip of claim 1, including athird component which requires a clock having a relatively small delaywith respect to said system clock, said relatively small delay beingless than one-half of said clock period, said integrated circuit chipalso including a second delay element substantially equal to saidrelatively small delay, said integrated circuit chip further includingmeans for coupling the output of said phase-locked-loop to said thirdcomponent via a third path which includes both said second delay elementand said first-mentioned delay element, said third path providing thesame delay as said first path except for said second delay element. 3.The integrated circuit chip of claim 2, wherein each of said first,second and third paths comprise clock buffer paths providing the samedelay.
 4. The integrated circuit chip of claim 3, wherein each clockbuffer path includes a plurality of inverters.
 5. The integrated circuitchip of claim 2, wherein one of said components comprises a flip-flopand another component comprises a RAM.
 6. The integrated circuit chip ofclaim 2, wherein one of said components comprises a latch and anothercomponent comprises a RAM.
 7. The integrated circuit chip of claim 3,wherein one of said components comprises a latch and another componentcomprises a flip-flop.
 8. The integrated circuit chip of claim 2,wherein said chip is a VLSI chip.
 9. The integrated circuit chip ofclaim 2, wherein said components are responsive to the rising edges ofthe respective clocks applied thereto.
 10. The integrated circuit chipof claim 2, wherein said delay elements are provided byserially-connected inverters.